HPS Peripheral FPGA Clocks parameters - HPS Peripheral FPGA Clocks parameters Cyclone V Hard Processor System Technical Reference Manual 2021.07.08 states “If I2C 2 peripheral is routed to FPGA, use the input field to specify I2C 2 output clock frequency” In Quartus Platform designer the options for this clock, FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK, are in the range 1 to 1000MHz. However I would expect an I2C-bus to operate at 100kHz or 400kHz. Why is the clock range limited to 1MHz? - How would I set 400kHz? Thank you Replies: Re: HPS Peripheral FPGA Clocks parameters Thanks @aikeu It sounds like you are saying that when Technical Reference Manual 2021.07.08 states on page 27-11 “If I2C 2 peripheral is routed to FPGA, use the input field to specify I2C 2 output clock frequency” it is meaning this field sets an input clock source frequency and not the output frequency on SCL. And that this input frequency is divided down by a value in register ic_con to get SCL frequency. Reading further in Technical Reference Manual I do see that it says "The I2C controller can operate in standard mode (with data rates of up to 100 Kbps) or fast mode (with data rates less than or equal to 400 Kbps)." Replies: Re: HPS Peripheral FPGA Clocks parameters We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Thanks. Regards, Aik Eu Replies: Re: HPS Peripheral FPGA Clocks parameters Hi emery, You can you can set the operating SCL output through the register ic_con, referring to the Cyclone V technical reference manual. The input clock source will be divided accordingly. Thanks. Regards, Aik Eu