What is the relationship between PHASEDONE and SCANCLK in the ALTPLL Intel® FPGA IP? - What is the relationship between PHASEDONE and SCANCLK in the ALTPLL Intel® FPGA IP? Description PHASEDONE deassertion (low) is synchronous to SCANCLK rising edge and PHASEDONE assertion (high) is asynchronous to SCANCLK in the ALTPLL Intel® FPGA IP. Resolution N/A Custom Fields values: ['novalue'] Troubleshooting - False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'HardCopy™ III ASIC Devices', 'HardCopy™ IV E ASIC Devices', 'HardCopy™ IV GX ASIC Devices', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']