Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power - Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power Description You may see the following warning when running the Design Assistant tool in Quartus II software on your compiled HPS design. Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power ; <hierarchy>:altdq_dqs2_inst|dqsbusout Resolution This warning is expected and can be safely ignored. Custom Fields values: ['novalue'] Troubleshooting 1408190367 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Arria® V GT FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']