Error: " Use clock enable for output ports are unavailable while output ports are not registered." - Error: " Use clock enable for output ports are unavailable while output ports are not registered." Description Due to a problem in the Quartus® II software version 14.0 Arria 10 Edition, you may see this error if you change the option from Two read/write ports to One read port and one write port using the same parameter editor. This problem affects any designs that use One read port and one write port with Use clock enable for output registers even though the output port is already registered. Resolution To work around this problem, close the RAM: 2-PORT IP parameter editor, then reopen it. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']