Why is the Intel® Arria® 10 PHYLite IP core interface_locked signal not asserted? - Why is the Intel® Arria® 10 PHYLite IP core interface_locked signal not asserted? Description Due to a known limitation in the Intel® Arria® 10 PHYLite IP, the interface_locked signal will not assert when all odd-numbered index pins in an I/O lane are unused as data pins. However, the Intel® Arria® 10 PHYLite IP is fully functional for data transfers. Resolution To work around this problem, use at least one odd-numbered index pin in an I/O lane (such as pin_index 1, 3, 5 … 11) for the data pins in your Intel® Arria® 10 PHYLite design. Custom Fields values: ['novalue'] Troubleshooting 14012315634 True ['PHY Lite for Parallel Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 17.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']