Why is the RX Core FIFO full if PMA and PCS bonding mode is enabled in H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP? - Why is the RX Core FIFO full if PMA and PCS bonding mode is enabled in H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP? Description Due to a problem with Quartus® Prime Pro Edition Software version 17.1, the H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP may output incorrect rx_clkout frequency if the PMA and PCS bonding mode is enabled for non-PCIe mode. The incorrect rx_clkout frequency will cause the RX Core FIFO to become full. Resolution Use PMA-only bonding for non-PCIe mode . This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.1. Custom Fields values: ['novalue'] Troubleshooting FB: 549014; False ['L-Tile H-Tile Transceiver Native PHY Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']