Why can't the fractional PLL (fPLL) parameters be changed using the Resource Property Editor or Chip Planner when targeting Stratix® V, Arria® V, or Cyclone® V devices? - Why can't the fractional PLL (fPLL) parameters be changed using the Resource Property Editor or Chip Planner when targeting Stratix® V, Arria® V, or Cyclone® V devices? Description It is not possible to edit the parameters of fPLLs using the Resource Property Editor or Chip Planner in the Quartus® II software when designing with Stratix® V, Arria® V, or Cyclone® V devices. Resolution Utilize the PLL Reconfiguration feature to dynamically update the fPLL parameters. For further details, refer to AN661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions (PDF) Custom Fields values: ['novalue'] Troubleshooting 69258 False ['Arria® V Transceiver PLL IP'] ['FPGA Dev Tools Quartus II Software'] novalue No plan to fix ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']