Why do the values of the TLPBYPASS_ERR_STATUS status register of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express persist after a system level warm reset? - Why do the values of the TLPBYPASS_ERR_STATUS status register of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express persist after a system level warm reset? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 and earlier, the values stored in the TLPBYPASS_ERR_STATUS status register of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express will persist after a system warm reset (pin_perst event) or hot reset. A cold reset (power cycle) will clear the content of the TLPBYPASS_ERR_STATUS status register. Resolution To work around this problem, clear the TLPBYPASS_ERR_STATUS status register (offset 0x1310) after a warm reset using the Hard IP Reconfiguration Interface (pX_hip_reconfig_*) . Note that the Hard IP Reconfiguration Interface is 8-bit wide, making at least 3 write operations necessary to clear all the bits from the TLPBYPASS_ERR_STATUS status register. This problem is fixed in the Intel® Quartus® Prime Pro Edition Software v22.1. Custom Fields values: ['novalue'] Errata 1509615739 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 21.1 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']