Why is RxErr status asserted after asserting the ports "pld_clrpcs_n[1:0]" while using the P-Tile Intel® FPGA IP for PCI Express? - Why is RxErr status asserted after asserting the ports "pld_clrpcs_n[1:0]" while using the P-Tile Intel® FPGA IP for PCI Express? Description The RxErr status will be asserted after reseting the P-Tile Intel® FPGA IP for PCI Express with the pld_clrpcs_n[1:0] ports. Resolution According to the PCI Express Base specification revision 4.0 version 1.0, sticky registers including RxErr status are not cleared after any type of conventional reset (cold, warm, or hot). Clear the RxErr status in the PCI Express configuration space register before checking the RxErr status during data transaction. This behaviour will not be changed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15010651986 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 21.4 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']