Why is the function simulation behavior incorrect when there are multiple RAM: 2-Port Intel FPGA IPs? - Why is the function simulation behavior incorrect when there are multiple RAM: 2-Port Intel FPGA IPs? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.1, function simulation behavior may be incorrect when your design contains multiple RAM-2 Port IPs enabling "Emulate TDP dual clock mode" and running the auto generated simulation script. The multiple RAM IPs all instantiate dcfifo_in and dcfifo_out submodules with the same module name. But each IP’s dcfifo_in and dcfifo_out files instantiate different submodules. In the simulation script, all dcfifo_in, dcfifo_out and their submodules files of different RAM IPs are compiled into the same simulation library. Therefore, the later compiled dcfifo_in and dcfifo_out files overwrite the previous ones. All RAM IPs use the same dcfifo_in and dcfifo_out modules and lead to the incorrect simulation behavior. Resolution To workaround this problem, modify the simulation script in sim/common/<simulation tool>_files.tcl to create different libraries for different RAM IPs and compile dcfifo_in and dcfifo_out instances into different libraries correspondingly. Original script: proc get_design_libraries {} { set libraries [dict create] dict set libraries fifo_191 1 dict set libraries ram_2port_191 1 dict set libraries dpram32x512 1 dict set libraries dpram16x1024 1 return $libraries} proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} { lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram32x512/dpram32x512/ram_2port_191/sim/dcfifo_in.v"]\" -work ram_2port_191 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram32x512/dpram32x512/ram_2port_191/sim/dcfifo_out.v"]\" -work ram_2port_191 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram32x512/dpram32x512/ram_2port_191/sim/dpram32x512_ram_2port_191_6nqqinq.v"]\" -work ram_2port_191 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram32x512/dpram32x512/ram_2port_191/sim/tdp_dpram32x512_ram_2port_191_6nqqinq.v"]\" -work ram_2port_191 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram16x1024/dpram16x1024/ram_2port_191/sim/dcfifo_in.v"]\" -work ram_2port_191 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram16x1024/dpram16x1024/ram_2port_191/sim/dcfifo_out.v"]\" -work ram_2port_191 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram16x1024/dpram16x1024/ram_2port_191/sim/dpram16x1024_ram_2port_191_u7jjoxa.v"]\" -work ram_2port_191 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram16x1024/dpram16x1024/ram_2port_191/sim/tdp_dpram16x1024_ram_2port_191_u7jjoxa.v"]\" -work ram_2port_191 " return $design_files } Modified script: proc get_design_libraries {} { set libraries [dict create] dict set libraries fifo_191 1 dict set libraries ram_2port_191_0 1 dict set libraries ram_2port_191_1 1 dict set libraries dpram32x512 1 dict set libraries dpram16x1024 1 return $libraries} proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} { lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram32x512/dpram32x512/ram_2port_191/sim/dcfifo_in.v"]\" -work ram_2port_191_1 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram32x512/dpram32x512/ram_2port_191/sim/dcfifo_out.v"]\" -work ram_2port_191_1 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram32x512/dpram32x512/ram_2port_191/sim/dpram32x512_ram_2port_191_6nqqinq.v"]\" -work ram_2port_191_1 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram32x512/dpram32x512/ram_2port_191/sim/tdp_dpram32x512_ram_2port_191_6nqqinq.v"]\" -work ram_2port_191_1 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram16x1024/dpram16x1024/ram_2port_191/sim/dcfifo_in.v"]\" -work ram_2port_191_0 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram16x1024/dpram16x1024/ram_2port_191/sim/dcfifo_out.v"]\" -work ram_2port_191_0 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram16x1024/dpram16x1024/ram_2port_191/sim/dpram16x1024_ram_2port_191_u7jjoxa.v"]\" -work ram_2port_191_0 " lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/dpram16x1024/dpram16x1024/ram_2port_191/sim/tdp_dpram16x1024_ram_2port_191_u7jjoxa.v"]\" -work ram_2port_191_0 " return $design_files} This problem is fixed beginning with version 19.3 of the Intel® Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 1507330485/1507119241 False ['RAM 2-PORT IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']