Why does TimeQuest not analyze the tx_enable and tx_inclock or rx_enable and rx_inclock timing paths when using the ALTLVDS megafunction in external PLL mode? - Why does TimeQuest not analyze the tx_enable and tx_inclock or rx_enable and rx_inclock timing paths when using the ALTLVDS megafunction in external PLL mode? Description TimeQuest does not analyze the tx_enable and tx_inclock or the rx_enable and rx_inclock timing paths when using the ALTLVDS megafunction in external PLL mode. These paths use dedicated routing, so as long as the phase shifts are set correctly on the PLL output clocks used by the ALTLVDS megafunction, Altera will guarantee the timing between these paths. Related Articles How do I calculate the frequency, phase shift and duty cycle for clocking ALTLVDS soft SERDES using external PLL mode? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® GX FPGA', 'Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'HardCopy™ III ASIC Devices', 'HardCopy™ IV E ASIC Devices', 'HardCopy™ IV GX ASIC Devices', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']