Are any hardened device features allowed in the core partition in a Configuration via Protocol (CvP) design? - Are any hardened device features allowed in the core partition in a Configuration via Protocol (CvP) design? Description No hardened features are allowed in the core partition in a CvP design. The following are some examples of hardened features which must reside in the periphery (top) partition: PLL JTAG interface Partial Reconfiguration (PR) block EDCRC block Internal Oscillator block On-Chip Termination control block Unique Chip ID ASMI block Remote Update block Altera Temperature Sensor Hard Memory Controller Hard IP for PCI Express Resolution The Quartus® Prime software will issue an error if any hardened features exist in a CvP core partition. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']