In DDR2 and DDR3 SDRAM Controller with UniPHY, Selecting VHDL Gives a Verilog HDL IP Core - In DDR2 and DDR3 SDRAM Controller with UniPHY, Selecting VHDL Gives a Verilog HDL IP Core Description If you select VHDL in the MegaWizard interface and generate a DDR2 or DDR3 SDRAM controller with UniPHY IP core, the generated core is in Verilog HDL. Resolution To generate a VHDL IP core follow these steps: In a text editor open < Quartus II directory > \ip\altera\uniphy\lib\common_ddrx.tcl . Search for the string " LANGUAGE " that appears in the following code: append param_str ",LANGUAGE=[get_generation_property HDL_LANGUAGE] " Change this line to the following code: append param_str ",LANGUAGE=vhdl" Continue searching for the next occurence of the string " LANGUAGE " which appears in the following code: if {[string compare -nocase [get_generation_property HDL_LANGUAGE] verilog] == 0} { add_file /.v {SYNTHESIS SUBDIR} puts "set_global_assignment -name VERILOG_FILE \[file join $::quartus(qip_path) .v\]" } else { add_file /.vhd {SYNTHESIS SUBDIR} puts "set_global_assignment -name VHDL_FILE \[file join $::quartus(qip_path) .vhd\]" } Comment out the if line, the else line, and the block of code in the conditional section so that the code in the " else " block always executes, similar to the following code: # if {[string compare -nocase [get_generation_property HDL_LANGUAGE] verilog] == 0} { # add_file /.v {SYNTHESIS SUBDIR} # puts "set_global_assignment -name VERILOG_FILE \[file join $::quartus(qip_path) .v\]" # } else { add_file /.vhd {SYNTHESIS SUBDIR} puts "set_global_assignment -name VHDL_FILE \[file join $::quartus(qip_path) .vhd\]" # } Use the MegaWizard interface to generate a UniPHY-based IP core. To generate a Verilog HDL IP core, restore the original common_ddrx.tcl file. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 10.1 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']