Why do both rx_clk and tx_clk output of the Intel® FPGA Triple-Speed Ethernet IP core stop after about 1.7 sec in the simulation? - Why do both rx_clk and tx_clk output of the Intel® FPGA Triple-Speed Ethernet IP core stop after about 1.7 sec in the simulation? Description Due to a problem with the simulation model of the Intel® FPGA Triple-Speed Ethernet IP core, both rx_clk and tx_clk output of the Intel® FPGA Triple-Speed Ethernet IP core stop after about 1.7 sec in the simulation. This is due to the MSB of the internal 32-bits clock counter not toggled. This problem can be seen in only simulation. Resolution There is no workaround for this problem. This problem is fixed starting with the Intel® Quartus® Prime Standard Edition software version 21.1. Custom Fields values: ['novalue'] Troubleshooting 22010710267 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 21.1 17.0 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']