Cannot Simulate Auto-Rate Negotiation for Some Line Rates in CPRI IP Core VHDL Models that Target Arria II GZ and Stratix IV GX Devices - Cannot Simulate Auto-Rate Negotiation for Some Line Rates in CPRI IP Core VHDL Models that Target Arria II GZ and Stratix IV GX Devices Description If you generate a VHDL simulation model for your CPRI MegaCore function that targets an Arria II GZ or Stratix IV GX device, you cannot use it to simulate auto-rate negotiation between the two CPRI line rates of 614.4 Mbps and 1228.8 Mbps. This issue affects all CPRI MegaCore function VHDL simulation models with auto-rate negotiation enabled that target an Arria II GZ or Stratix IV GX device. This issue affects simulation only. Resolution This issue has no workaround. To simulate auto-rate negotiation between the two CPRI line rates of 614.4 Mbps and 1228.8 Mbps, generate and simulate a Verilog HDL simulation model. This issue is fixed in version 11.1 of the CPRI MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.1 11.0 ['Arria® II FPGAs', 'Stratix® IV FPGAs'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25