Error: Internal error: (<signal name> => <signal name>) Internal error: standard logic: std_logic ports/signals must be width 1 but was <n> - Error: Internal error: (<signal name> => <signal name>) Internal error: standard logic: std_logic ports/signals must be width 1 but was <n> Description Due to a problem in the Quartus® Prime Pro Edition Software version 18.1 Update 1 and earlier, you may see this error when generating a Platform Designer system. This error occurs when the Platform Designer system includes a generic component. Resolution To work around this problem, select the component in Platform Designer and then select the component instantiation tab. Change the width of each signal to 1, then revert the width back to its original value and generate the HDL. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 1806993729 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.1 18.1.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']