Why is the input data rate parameter text box not present in the ALTLVDS_RX Intel® FPGA IP in the Quartus® II software version 13.0sp1? - Why is the input data rate parameter text box not present in the ALTLVDS_RX Intel® FPGA IP in the Quartus® II software version 13.0sp1? Description In the Quartus® II software version 13.0, the input data rate text box was available when using external phase-locked lioop (PLL) mode with DPA enabled in the ALTLVDS_RX Intel® FPGA IP. Resolution Beginning with version 13.0sp1, the fitter automatically derives the data rate from the associated PLL Intel FPGA IP settings. Custom Fields values: ['novalue'] Troubleshooting 1408188715 False ['ALTLVDS_RX'] ['novalue'] novalue novalue ['Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']