Error: Could not find a location with: OCT_CAL_BLOCK_ID - Error: Could not find a location with: OCT_CAL_BLOCK_ID Description When compiling a design with multiple UniPHY-based DDR2 or DDR3 memory controllers in the Quartus® II software version 12.1, you may experience the following error: Error : Illegal constraint of pin to the region (X1, Y1) to (X2, Y2): no valid locations in region Info : The pin name: mem_ck Info : The I/O pad is constrained to the location PIN_NUM due to: User Location Constraints (PIN_NUM) Error: Could not find a location with: OCT_CAL_BLOCK_ID of 2 (1 location affected) Info: pin containing PIN_NUM The error is generated because the mem_ck pin is assigned to the wrong OCT termination control block. Resolution The workaround is to add the following termination control block assignment to the QSF file or Assignment Editor: set_instance_assignment -name TERMINATION_CONTROL_BLOCK “<hierarchy>|altera_mem_if_oct_stratixv:oct0|sd1a_0" -to mem_ck* This issue has been fixed in the Quartus® II software 14.1 version. Related Articles Error (175005): Could not find a location with: OCT_CAL_BLOCK_ID of <block ID number> (<number of pins> locations affected) Error (181011): Incompatible on-chip termination settings detected for pins in the DQS group fed by DQS I/O pin <QK clock pin>. All pins in group must use the same OCT control block. Error (175001): Could not place HPHY When using UniPHY IP in Stratix V devices, what are the options for changing the calibrated OCT termination values from the default values ? Custom Fields values: ['novalue'] Troubleshooting 2205821762 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] 14.1 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']