Is there a longer delay on VREF pins when used as I/O compared to general purpose I/O pins in Cyclone-series devices that support dual-purpose VREF pins? - Is there a longer delay on VREF pins when used as I/O compared to general purpose I/O pins in Cyclone-series devices that support dual-purpose VREF pins? Description Yes, there is a longer delay on VREF pins when used as an I/O pin compared to a general purpose I/O pin in Cyclone®-series devices that support dual-purpose VREF pins. The pin capacitance is higher on VREF pins than general purpose I/O pins, thus you should avoid placing fast edge rate signals such as clocks on these pins, and avoid using these pins in buses since the I/O timing will not be consistent with the rest of the bus. Related Articles Warning (11106): Shared VREF <pin number> is used as GPIO <pin name>. This action reduces fmax performance. If I am using voltage referenced I/O standards in Cyclone through Cyclone IV devices, can any of the VREF pins be used as I/O pins in an I/O bank containing voltage referenced input pins? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Cyclone® FPGAs', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']