Error (169026): Pin oct_rzqin is incompatible with I/O bank {bank}. It uses I/O standard SSTL-135, which has VCCIO requirement of 1.35V. The requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in using VCCIO 2.5V. - Error (169026): Pin oct_rzqin is incompatible with I/O bank {bank}. It uses I/O standard SSTL-135, which has VCCIO requirement of 1.35V. The requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in using VCCIO 2.5V. Description This error might happen if you are trying to implement DDR3L SDRAM interface using UniPHY based controller IP. DDR3L SDRAM interface uses SSTL-1.35V I/O standard, the oct_rzq pin also requires the SSTL-1.35V I/O standard. Error (169026): Pin oct_rzqin is incompatible with I/O bank {bank}. It uses I/O standard SSTL-135, which has VCCIO requirement of 1.35V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 2.5V. Resolution Make the following assignment manually in your project QSF file: set_instance_assignment -name IO_STANDARD "SSTL-135" -to oct_rzqin Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']