Why am I seeing the below mask error for R-Tile Avalon® Streaming FPGA IP for PCI Express Gen4 (16GT/s) when running the Lane Margining tool in Debug Toolkit? - Why am I seeing the below mask error for R-Tile Avalon® Streaming FPGA IP for PCI Express Gen4 (16GT/s) when running the Lane Margining tool in Debug Toolkit? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you may see the below mask error during R-tile PCIe Gen4 (16.0GT/s) electrical lane margining test. Resolution To address this, update the margin reference validation data as follows: 4.64ps for 1e-9 and 6.13ps for 1e-12 corresponding to an estimated end-to-end channel loss of 18db @ 8GHz (16.0GT/s). These data are scheduled to be updated in a future release of Quartus® Prime Pro Edition software version and R-Tile Avalon® Streaming IP for PCI Express User Guide. Note : The margin reference validation data is based on the Intel® Eagle Stream platform with an internal validation board (at PCIe slot B) whose total insertional loss range from 33dB to 36dB @ 16GHz (32.0GT/s) based on PCIe Base spec 5.0 (from lane0 to lane15). Your system design may differ, and therefore these margin references are estimates and subject to change. Related IP Cores AXI Multichannel DMA IP for PCI Express AXI Streaming IP for PCI Express R-tile Avalon Streaming IP for PCI Express R-tile Switch IP for PCI Express Custom Fields values: ['novalue'] Troubleshooting 15018709456 novalue ['Interfaces PCIe Multi-Channel DMA AXI (Primary)', 'Interfaces PCIe'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']