Why are the ~OBSERVABLE output ports of the transceiver blocks in my design reported as unconstrained for hold analysis? - Why are the ~OBSERVABLE output ports of the transceiver blocks in my design reported as unconstrained for hold analysis? Description The Quartus® II software version 9.1 SP1 and earlier may not automatically constrain ~OBSERVABLE output ports such as ~OBSERVABLERXANALOGRESET in Stratix® IV GX transceiver blocks for hold analysis. The derive_pll_clocks command adds only set_max_delay assignments to the output ports for setup analysis and does not make the corresponding set_min_delay assignments required for hold analysis. To constrain the output ports for hold analysis, add the following set_min_delay command for the ~OBSERVABLE output ports: set_min_delay 0 -to [get_ports <OBSERVABLE outputs>] This problem is scheduled to be fixed in a future version of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']