What is the read latency of an M20K ROM that must be accounted for when performing MIF-based streaming dynamic reconfiguration in Stratix® V GX devices? - What is the read latency of an M20K ROM that must be accounted for when performing MIF-based streaming dynamic reconfiguration in Stratix® V GX devices? Description When implementing MIF-based dynamic reconfiguration on Stratix® V GX devices, and reading data from an M20K based ROM, the read latency is one clock cycle if the ROM output is unregistered, or two clock cycles if the output is registered. Resolution This problem is fixed in the Quartus® software version 12.0. Custom Fields values: ['novalue'] Troubleshooting FB : 37524 False ['novalue'] ['novalue'] novalue novalue ['Stratix® V FPGAs', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']