Arria V GZ Hard IP for PCI Express Qsys Example Design Shows Incorrect Connection for Transceiver Reconfiguration Controller Reset - Arria V GZ Hard IP for PCI Express Qsys Example Design Shows Incorrect Connection for Transceiver Reconfiguration Controller Reset Description The following Qsys example designs for the Arria V GZ Hard IP for PCI Express IP Core shows two reset outputs driving the reset input to the Transceiver Reconfiguration Controller mgmt_rst_reset port: Gen1 x4, Gen1 x8, Gen2 x1, and Gen2 x4. Resolution This is issue is fixed in version 13.1 Update 1 of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1.1 13.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']