Why does my F-tile Ethernet Intel® FPGA Hard IP design example simulation fail using the Questa*-Intel® FPGA Edition simulator? - Why does my F-tile Ethernet Intel® FPGA Hard IP design example simulation fail using the Questa*-Intel® FPGA Edition simulator? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, 22.3, and 22.4, you might see the F-tile Ethernet Intel® FPGA Hard IP design example simulation gets stuck at the reset sequence using the Questa*-Intel® FPGA Edition simulator. Resolution There is no workaround. You can use other simulators to run the simulation. For example, ModelSim* SE or QuestaSim*. This problem is fixed in version 23.1 of Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 16016498230 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.2 ['Agilex™ 7 FPGA I-Series'] ['Simulation Dev Tools Questa'] ['novalue'] ['novalue']