Why are packet counters rolling over within the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP? - Why are packet counters rolling over within the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, the packet counters within the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP will roll over when small back-to-back packets are encountered, and the packet counters are nearing the saturated value (i.e., all F’s). Resolution There is no workaround for this problem. This problem has been fixed in version 23.2 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 16020064102, 16019179800 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 23.1 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']