Why does the simulation of the F-Tile Serial Lite IV FPGA IP design with simplex PMA mode fail? - Why does the simulation of the F-Tile Serial Lite IV FPGA IP design with simplex PMA mode fail? Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.4, you may observe that the simulation of the F-Tile Serial Lite IV IP design will fail with the following configuration: OPN: Agilex™ F-Tile devices with OPNs that end with the suffix VR0, VR1, and VR2 Simulation mode: Slowsim PMA modulation type: NRZ PMA type: FGT PMA data rate: 17.4 Gbps PMA mode: TX/RX Number of PMA lanes: >=14 This problem is due to the clock frequency generated by the simulation model having a high deviation from the expected frequency, which causes FIFO empty or FIFO overflow. Resolution To work around this problem, you can adopt the following two methods: Change the OPN: Agilex ™ F-Tile devices with OPNs that end with the suffix VR3 and AA . Change the simulation mode from Slowsim to Fastsim . Custom Fields values: ['novalue'] Troubleshooting 15012327916 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']