FPGA example design for Agilex 7 with HPS connected to SDRAM - FPGA example design for Agilex 7 with HPS connected to SDRAM I am trying to create design for the Agilex HPS SDRAM and I'm running into issues. Does anyone have any experience with this and may be know where i can find design example? I found some references but not acurate, so i could not follow them. Thanks, Replies: Re: FPGA example design for Agilex 7 with HPS connected to SDRAM Hi Albert, There are two KDBs that you can refer to workaround the error. https://www.intel.com/content/www/us/en/support/programmable/articles/000086164.html https://www.intel.com/content/www/us/en/support/programmable/articles/000088060.html You can submit a new thread to continue the discussion on this issue as this thread is discuss for different question and marked as solved already. I will close this thread. Regards, Adzim Replies: Re: FPGA example design for Agilex 7 with HPS connected to SDRAM Can i ask another q on same issue. I also trying to simulate design with questa simulator. I did generate TB and was able compile, but getting error: Error: (vsim-8388) Could not find the MVC shared library : MvcHome directory '' is not a valid MV Been told that i need QVIP license that include with Altera FPGA license, but i am not able find instructions how to set it up. Probably i should post new Q. Please let me know if you know how to resolve this. Thanks again. Replies: Re: FPGA example design for Agilex 7 with HPS connected to SDRAM Got it, Still why no references at Intel site for this arrangement. I could not find this on my own, glad that Adzim reply. In any case it's resolved. Thanks. Replies: Re: FPGA example design for Agilex 7 with HPS connected to SDRAM Because Rocketboards was set up as a dedicated site for HPS designs and code. It's been like that since the first HPS devices in 2012/2013. Replies: Re: FPGA example design for Agilex 7 with HPS connected to SDRAM This is understood able, what i meant is why Intel do not provide any HSP design reference on Intel side. You can find plenty references designs for Nios but not for HPS. Thanks, Replies: Re: FPGA example design for Agilex 7 with HPS connected to SDRAM All HPS-related design examples and code are at Rocketboards, so you won't find them at the Intel web site. Replies: Re: FPGA example design for Agilex 7 with HPS connected to SDRAM Hi Adzim, I wish I could find it on my own. This is what I looked at and I am wondering why no similar reference designs are available at Intel site. I am in the process of building it with Quartus version 24.1.0. Successfully complete updating all IP's and waiting for completion. Again thanks. Albert, Replies: Re: FPGA example design for Agilex 7 with HPS connected to SDRAM Hello, May I know what is the issue that you're facing? Have you checked the HPS example design from RocketBoards website? https://www.rocketboards.org/foswiki/Documentation/HPSExampleDesignForAgilex7ISeriesDeKit2xRTileAnd1xFTile Regards, Adzim