Why does the Intel® Quartus® Prime software report lower PLL VCO frequency than the PLL specifications for Arria® V, Cyclone® V, and Stratix® V devices? - Why does the Intel® Quartus® Prime software report lower PLL VCO frequency than the PLL specifications for Arria® V, Cyclone® V, and Stratix® V devices? Description The Intel® Quartus® Prime software may report lower PLL VCO frequency than the PLL specifications for Arria® V, Cyclone® V, and Stratix® V devices in the following items. Altera PLL IP parameter editor > Advanced Parameters tab > PLL Output VCO Frequency Compilation Report > Fitter > Resource Section > PLL Usage Summary > PLL VCO Frequency This is because a PLL in Arria V, Cyclone V, or Stratix V devices have a VCO post divider and the Intel Quartus Prime software reports VCO frequency after the VCO post divider. The raw VCO frequency before the VCO post divider meets the PLL specifications. You can calculate the raw VCO frequency as follows: << Example 1 >> Device : Cyclone V -C6, -C7, -I7 speed grades PLL voltage-controlled oscillator (VCO) operating range : Min 600MHz, Max 1600MHz Altera PLL IP parameters : Reference Clock Frequency = 10.0 MHz Output Clocks outclk0 Desired Frequency = 300.0 MHz Actual Frequency = 300.0 MHz M, N, C, VCO post divider counter and PLL output VCO frequency are calculated as follows: M counter = 30 N counter = 1 C counter = 1 VCO Post Divide Counter = 2 PLL Output VCO Frequency = Reference Clock Frequency * M / N / C = 10MHz * 30 / 1 / 1 = 300MHz The raw VCO frequency before VCO post divider = PLL Output VCO Frequency * VCO Post Divide Counter = 300MHz * 2 = 600MHz << Example 2 >> Device : Cyclone V -C6, -C7, -I7 speed grades PLL voltage-controlled oscillator (VCO) operating range : Min 600MHz, Max 1600MHz Altera PLL IP parameters : Reference Clock Frequency = 10.0 MHz Output Clocks outclk0 Desired Frequency = 600.0 MHz Actual Frequency = 600.0 MHz M, N, C, VCO post divider counter and PLL output VCO frequency are calculated as follows: M counter = 60 N counter = 1 C counter = 1 VCO Post Divide Counter = 1 PLL Output VCO Frequency = Reference Clock Frequency * M / N / C = 10MHz * 60 / 1 / 1 = 600MHz The raw VCO frequency before VCO post divider = PLL Output VCO Frequency * VCO Post Divide Counter = 600MHz * 1 = 600MHz Custom Fields values: ['novalue'] Troubleshooting 1507020410 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']