Verilog HDL simulation model for ALTERA_FP_MATRIX_MULT IP core produces incorrect simulations - Verilog HDL simulation model for ALTERA_FP_MATRIX_MULT IP core produces incorrect simulations Description Because of a problem with the Verilog HDL simulation model for the ALTERA_FP_MATRIX_MULT IP core, the simulation output is incorrect. This problem affects the NCSim software only. Resolution Use the VHDL simulation model Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']