Why Qsys pick the wrong parameters value of FIR Compiler II and create an error message when generate the Qsys system? - Why Qsys pick the wrong parameters value of FIR Compiler II and create an error message when generate the Qsys system? Description You may receive the following error message when your Qsys design consist of more than one FIR Compiler II and which are located at difference Qsys subsystem with difference parameter. Error: fir_compiler_ii_0: Port ast_sink_data has width 32 in TCL, but 16 in the design file This issue is causing by FIR Compiler II using global variables to avoid re-querying parameters. This works fine if there is just a single instance of FIR complier II. Resolution To fix this issue, all of the global variables in the HP_FIR_HW.tcl file have to removed and this will officially fixed in version 12.1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']