Pin Planner HDL Syntax Error - Pin Planner HDL Syntax Error Description There is an HDL syntax error in Pin Planner-generated top-level design files that contain a DDR or DDR2 SDRAM Controller variation. Pin Planner-generated top-level design files that use a design that contains a DDR or DDR2 SDRAM Controller variation. If you import the DDR or DDR2 SDRAM Controller Pin Planner file into Pin Planner and then generate a top-level design file for your design, it contains an HDL syntax error and does not compile in the Quartus II software. You cannot use this top -level design file for IO Assignment Analysis. Resolution Use the IP Toolbench top-level example design and automatically assigned constraints to verify your pin and IO assignments. This issue will not be fixed. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']