Why is my Stratix IV Hard IP for PCI Express VHDL altpcierd_write_dma_requester_128.vhd different from its Verilog counterpart? - Why is my Stratix IV Hard IP for PCI Express VHDL altpcierd_write_dma_requester_128.vhd different from its Verilog counterpart? Description The Stratix IV® Hard IP for PCI Express® in VHDL has an inconsistency from its Verilog HDL counterpart. This inconsistency can cause errors in a PCIe design for certain addresses on the TX interface. Resolution In altpcierd_write_dma_requester_128.vhd at line 1036 change: tx_desc_addr <= tx_desc_addr_pipe; to tx_desc_addr <= tx_desc_addr tx_length_byte_32ext; Related Articles Why is the addressing incorrect for the CRA port on the Hard IP for PCI Express? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® IV FPGAs', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']