Why does the Nios® V processor that applies fast JTAG UART driver stop (stuck in a loop) when the JTAG UART terminal is not active? - Why does the Nios® V processor that applies fast JTAG UART driver stop (stuck in a loop) when the JTAG UART terminal is not active? Description Due to a problem in the Board Support Package Editor of Quartus ® Prime software, the JTAG UART driver for fast implementation might get stuck in a loop for any Nios ® V processor designs, when JTAG UART terminal is not active. This problem has been present since: Quartus ® Prime Pro Edition software version 21.3 Quartus ® Prime Standard Edition software version 22.1 It is because the JTAG UART IP is initialized before the Nios ® V processor initialization in alt_sys_init.c. For example: void alt_sys_init( void ) { ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); INTEL_NIOSV_M_INIT (NIOS, nios); } Resolution To work around this problem, update the alt_sys_init.c to initialize the Nios ® V processor first. void alt_sys_init( void ) { INTEL_NIOSV_M_INIT (NIOS, nios); ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); } This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime software. Additional Information Refer to Embedded Peripherals IP User Guide [titled as JTAG UART Core - Driver Options: Fast vs. Small Implementations] for more information about the JTAG UART driver for fast (non-blocking) and slow (blocking) implementation. Related Article NIOSV firmware stuck when juart-terminal is not open for the print messages. Custom Fields values: ['novalue'] Troubleshooting 14025316279 novalue ['Soft Embedded Processors RISC-V NIOS V (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 21.3 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Arria® V FPGAs and SoCs', 'Arria® II FPGAs', 'Cyclone® 10 GX FPGA', 'Cyclone® 10 LP FPGA', 'Cyclone® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'MAX® 10 FPGAs', 'MAX® V CPLDs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs', 'Stratix® IV FPGAs', 'MAX® II CPLDs'] ['novalue'] ['novalue'] ['novalue']