Macros with arguments and default value in SystemVerilog - Macros with arguments and default value in SystemVerilog It seems Quartus Prime can't support default value in a macro, i.e., the following code will report error with illegal character in macro parameter near "='0)" using standard version 18.1. However if i remove the default value (which is ='0 ) from the macro then there will be no complaints from the compiler. We would like to keep the default value so that we can use this macro with`ffr_arst(somereg_q,somereg_d,clk_i, rst_i) for most of our cases. May i know if there is a solution for this? `ifndef ffr_arst `define ffr_arst(Q, D, Clk, Rst, InitValue ='0 ) \ initial Q = InitValue; \ always_ff @(posedge Clk or posedge Rst) begin \ Q <= (Rst) ? InitValue : D; \ end `endif `ffr_arst(somereg_q,somereg_d,clk_i, rst_i,'0) Replies: Re: Macros with arguments and default value in SystemVerilog Thank you @ShengN_Intel , that answered my question. Replies: Re: Macros with arguments and default value in SystemVerilog Hi @uea999 , This feature is supported in pro version but not standard version check image below: Hopefully answering your doubts. Thanks, Best regards, Sheng p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.