Error(13305): Verilog HDL error at altera_eth_tse.v(138): can't find port "system_pll_clk_link" - Error(13305): Verilog HDL error at altera_eth_tse.v(138): can't find port "system_pll_clk_link" Description When generating the TSE example design with the following settings: Variant : 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver Target Board : Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit You might encounter a compilation error during the Support Logic Generation step: Error(13305): Verilog HDL error at altera_eth_tse.v(138): can't find port "system_pll_clk_link" Resolution The error occurs due to incorrect IP core configuration while generating the example design for F-Tile. To resolve this issue, ensure the following configuration steps are followed: Use the correct Preset when generating the example design. Library: 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and PMA (Agilex F-Tile) Using the preset ensures the IP core is properly configured for the target platform. In the Triple-Speed Ethernet IP Parameters tab: Under PCS Options, enable : Enable SGMII bridge Under F-Tile FGT Transceiver Options, enable : Enable F-Tile transceiver dynamic reconfiguration (System Clock Mode) Custom Fields values: ['novalue'] Troubleshooting 15015083662 False ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']