How is the Intel® Stratix® 10 DDR4 IP chip select signals mapped for the top and bottom memory devices in a clamshell topology? - How is the Intel® Stratix® 10 DDR4 IP chip select signals mapped for the top and bottom memory devices in a clamshell topology? Description When the clamshell topology is enabled in the Intel® Stratix® 10 DDR4 IP Parameter Editor, each rank requires two CS pins to configure the top and bottom memory chips separately. The following content shows how to map the CS pins from FPGA to memory chips in single-rank and dual ranks designs. Resolution For single-rank components: The Top (non-mirrored) components, FPGA_CS0, goes to MEM_TOP_CS0 The bottom (mirrored) components, FPGA_CS1, goes to MEM_BOT_CS0 For Dual-Rank components: The Top (non-mirrored) components, FPGA_CS0 goes to MEM_TOP_CS0 and FPGA_CS1 goes to MEM_TOP_CS1 The bottom (mirrored) components, FPGA_CS2 goes to MEM_BOT_CS0 and FPGA_CS3 goes to MEM_BOT_CS1 Custom Fields values: ['novalue'] Troubleshooting 1507195156 False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']