Why do 3.3V LVTTL/ LVCMOS input pins have the 3.3V LVTTL/ LVCMOS output IBIS model assigned to them for IBIS models generated by the Quartus® II software? - Why do 3.3V LVTTL/ LVCMOS input pins have the 3.3V LVTTL/ LVCMOS output IBIS model assigned to them for IBIS models generated by the Quartus® II software? Description The Quartus® II software will assign a 3.3V LVTTL/ LVCMOS output IBIS model for an input pin, if you have the PCI clamp diode enabled. The 3.3V LVTTL/ LVCMOS output IBIS model includes the 3.3V LVTTL/LVCMOS input buffer information. For example, you may see the “ttl33_cio_d4ps3” output IBIS model assigned to the 3.3V LVTTL input pin with PCI clamp diode enabled. You can simulate input functionality with this model. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']