Why is the output frequency of xcvr_recovered_clk not equal to 380.16MHz as described in the CPRI FPGA IP User Guide when using the E-Tile CPRI FPGA IP? - Why is the output frequency of xcvr_recovered_clk not equal to 380.16MHz as described in the CPRI FPGA IP User Guide when using the E-Tile CPRI FPGA IP? Description Due to a mistake in the CPRI FPGA IP User Guide, when using the E-Tile CPRI FPGA IP, the frequency of xcvr_recovered_clk is not equal to the 380.16MHz as stated in the documentation; the correct frequency is 368.64MHz. Resolution This mistake will be fixed in a future release of the CPRI FPGA IP User Guide. Custom Fields values: ['novalue'] Troubleshooting 15016021022 False ['Interfaces Communications CPRI (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix No plan to fix ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']