Error: Verilog HDL syntax error at f_tile_soft_reset_ctrl_if_mux_vl.sv(592) near text if - Error: Verilog HDL syntax error at f_tile_soft_reset_ctrl_if_mux_vl.sv(592) near text if Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, the F-Tile source files use the SystemVerilog 2012 standard. Compiling the project with an earlier SystemVerilog standard version could result in this compilation syntax error. Resolution To work around this problem, follow these steps to change the Hardware Description Language of the project: 1. Go to Assignments > Settings > Verilog HDL Input 2. In 'Verilog version', select SystemVerilog-2012 3. Confirm the following QSF assignment is set to: set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2012 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14021951378 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 24.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']