Agilex™ 3 Ethernet FPGA Hard IP Register Map - The GTS Ethernet FPGA Hard IP contains a hardened Ethernet stack and synthesizable soft logic. It can support a 10G data rate with an optional Firecode FEC. The Agilex™ 3 Register Map provides a comprehensive set of registers for configuring and accessing both the Hard IP blocks and soft logic blocks. - 2026-03-10
Agilex 3_Ethernet_Hard IP_Register_Map.xlsx
- Version
- Current
- Product Type
- Device Families > Agilex Families > Agilex 3 > C-Series
- Resource Type
- Source Name
- UD