Agilex 5 Auto-Negotiation and Link Training for Ethernet FPGA IP Register Map - The GTS AN/LT IP contains a hardened AN/LT protocol stack and synthesizable soft logic. It supports up to 25Gbps data rate with various RS-FEC types. - 2026-06-03
Agilex5_ANLT_Register_Map_26.1.xlsx
- Version
- current
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- Device Families > Agilex Families > Agilex 5 > D-Series
- Device Families > Agilex Families > Agilex 5 > E-Series
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- UD