GTS Interlaken FPGA IP Register Map - This is the register map that is located in the IP Registers chapter of the GTS Interlaken FPGA IP User Guide. - 2024-04-01
GTS Interlaken IP Register Map.xlsx
- Version
- 24.1-3.0.0
- Product Type
- Device Families > Agilex Families > Agilex 5 > D-Series
- Device Families > Agilex Families > Agilex 5 > E-Series
- Resource Type
- Developer Resources > Register Maps
- Source Name
- UD