Clocked Video Genlock (CVG) Demo on Agilex™ 7 FPGA I-Series FPGA Development Kit Video - This video showcases the utilization of Video Connectivity IPs and other Altera® FPGA Video and Vision Processing suite IP cores. It explains the process of employing SDI and Clocked Video FPGA IP cores to create a personalized Genlocked design. - 2023-12-07
cvg-demo-on-agilex-7-fpga-i-series-devkit-video.mp4
- Version
- 1.0