CPRI FPGA IP Register Map - Register map for the CPRI FPGA IP. The CPRI IP core internal registers are accessible using the CPU interface, an Avalon Memory-Mapped interface which conforms to the Avalon Interface Specifications. - 2023-04-13
CPRI Intel FPGA IP Register Map.xlsx
- Version
- 23.1-1.0.0
- Product Type
- Device Families > Arria Families > Arria 10
- Device Families > Cyclone Families > Cyclone V
- Device Families > Stratix Families > Stratix 10
- Device Families > Stratix Families > Stratix V
- Device Families > Agilex Families > Agilex 7 > F-Series
- Device Families > Agilex Families > Agilex 7 > I-Series
- Device Families > Arria Families > Arria V
- Device Families > Agilex Families > Agilex 7 > M-Series
- Resource Type
- Developer Resources > Register Maps
- Source Name
- UD