Chip ID Reading Using Mailbox Avalon® ST Client FPGA IP in Agilex™ FPGAs - This video shows the method to perform chip ID reading by interfacing with AVST interface using Mailbox Avalon® ST Client FPGA IP in Agilex™ FPGA. For more information about Mailbox Avalon ST Client FPGA IP please refer to user guide at link below: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-avst-client-ag.pdf - 2020-12-09
chip-id-reading-using-mailbox-avalon-st-client-intel-fpga-ip-in-intel-agilex.mp4
- Version
- 1.0
- Product Type
- Device Families > Agilex Families > Agilex 7
- Device Families > Agilex Families > Agilex 7 > F-Series
- Device Families > Agilex Families > Agilex 7 > I-Series
- Device Families > Agilex Families > Agilex 7 > M-Series
- Resource Type
- Developer Resources > Videos > How To Videos
- Developer Training > How To Videos
- Source Name
- UD