Chip ID Reading Using Mailbox Avalon® ST Client FPGA IP in Agilex™ FPGAs - This video shows the method to perform chip ID reading by interfacing with AVST interface using Mailbox Avalon® ST Client FPGA IP in Agilex™ FPGA. For more information about Mailbox Avalon ST Client FPGA IP please refer to user guide at link below: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-avst-client-ag.pdf - 2020-12-09
chip-id-reading-using-mailbox-avalon-st-client-intel-fpga-ip-in-intel-agilex.mp4
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- 1.0