F-Tile Auto-Negotiation and Link Training FPGA IP Register Map - Register Map for the F-Tile Auto-Negotiation and Link Training FPGA IP, which contains a hardened AN/LT protocol stack and synthesizable soft logic. It supports up to 25Gbps data rate with various RS-FEC types. - 2026-04-09

Product Type

Device Families > Agilex Families > Agilex 7 > F-Series

Device Families > Agilex Families > Agilex 7 > I-Series

Device Families > Agilex Families > Agilex 7 > M-Series

Resource Type

Source Name

UD