F-Tile Ethernet FPGA Hard IP Register Map - The F-Tile Ethernet-based FPGA IP contains a hardened Ethernet protocol stack and synthesizable soft logic. Supports up to 400 Gbps data rate with various RS-FEC types. - 2025-04-24
F-Tile Ethernet _Hard IP_Register Map_24.3.1.xlsx
- Version
- 24.3.1
- Product Type
- Device Families > Agilex Families > Agilex 7 > F-Series
- Device Families > Agilex Families > Agilex 7 > I-Series
- Device Families > Agilex Families > Agilex 7 > M-Series
- Resource Type
- Developer Resources > Register Maps
- Source Name
- UD