Do I need to setup the Avalon-MM-to-PCI Express address translation tables when using 64-bit addressing for the Avalon-Memory Mapped Hard IP for PCI Express? - Do I need to setup the Avalon-MM-to-PCI Express address translation tables when using 64-bit addressing for the Avalon-Memory Mapped Hard IP for PCI Express? Description The Avalon-Memory Mapped Hard IP for PCI Express® supports 64-bit addressing. If you select 64-bit addressing, no address translation is necessary. As a consequence, the 'Avalon to PCIe Address Translation Settings' section of the GUI in Qsys disappears automatically after setting 'Avalon-MM address width' to 64-bit. Avalon-MM-to-PCI Express address translation tables in Control Register Access (CRA) space at address 0x1000–0x1FFF are not necessary for 64-bit addressing. Resolution Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V GX FPGA', 'Cyclone® V GX FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']