How should the configuration data be transmitted when using Fast Passive parallel (FPP) x8, x16 or x32 configuration modes, when using Raw Binary Files (.rbf)? - How should the configuration data be transmitted when using Fast Passive parallel (FPP) x8, x16 or x32 configuration modes, when using Raw Binary Files (.rbf)? Description The configuration data in the raw binary programming file is little endian. If the .rbf contains the byte sequence 02 1B EE 01 (as an exa mple) then see below on how this data should be transmitted in FPP x8, x16 or x32 modes respectively: a) In FPPx8 mode, the LSb (least significant bit) of a byte is BIT0, MSb (most significant bit) is BIT7. BYTE0 = 02 BYTE1 = 1B BYTE2 = EE BYTE3 = 01 D[7..0] D[7..0] D[7..0] D[7..0] 0000 0010 0001 1011 1110 1110 0000 0001 b) In FPPx16 mode, the first byte in the file is the LSB (least significant byte) of the configuration word, and the second byte is the MSB (most significant byte). WORD0 = 1B02 WORD1 = 01EE LSB: BYTE0 = 02 MSB: BYTE1 = 1B LSB: BYTE2 = EE MSB: BYTE3 = 01 D[7..0] D[15..8] D[7..0] D[15..8] 0000 0010 0001 1011 1110 1110 0000 0001 c) In FPPx32 mode, the first byte in the file is the LSB (least significant byte) of the configuration double word, and the fourth byte is the MSB (most significant byte). Double Word = 01EE1B02 LSB: BYTE0 = 02 BYTE1 = 1B BYTE2 = EE MSB: BYTE3 = 01 D[7..0] D[15..8] D[23..16] D[31..24] 0000 0010 0001 1011 1110 1110 0000 0001 Resolution Ensure you do not swap the upper bits or bytes and the lower bits or bytes when performing FPP configuration. Incorrectly sending the configuration data during the configuration process may cause unexpected behavior on the CONF_DONE signal. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']